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1CY7C1361A
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
Features
* * * * * * * * * * * Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V -5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSS at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Multiple chip enables for depth expansion: three chip enables for TA(GVTI)/A(CY) package version and two chip enables for B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions Address pipeline capability Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications JTAG boundary scan for B and T package version Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), , Burst Control Inputs (ADSC, ADSP and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). However, the CE2 chip enable input is only available for TA(GVTI)/A(CY) package version. Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs (DQa and DQb) along with BWa and BWb (no BWc, BWd, DQc, and DQd). For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The GVT71256B36 and GVT71512B18 operate from a +3.3V power supply. All inputs and outputs are LVTTL compatible.
* * * * * * *
Functional Description
The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The GVT71256B36/CY7C1361A and GVT71512B18/ CY7C1363A SRAMs integrate 262,144x36 and 524,288x18 SRAM cells with advanced synchronous peripheral circuitry
Selection Guide
7C1361A-150 7C1363A-150 71256B36-6 71512B18-6 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 6.0 400 10 7C1361A-133 7C1363A-133 71256B36-6.5 71512B18-6.5 6.5 360 10 7C1361A-117 7C1363A-117 71256B36-7 71512B18-7 7.0 320 10 7C1361A-100 7C1363A-100 71256B36-8 71512B18-8 8.0 270 10
www..com
www..com Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600 June 11, 2001
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
256K x 36 (CY7C1361A/GVT71256B36) Functional Block Diagram[1]
BYTE a WRITE
BWa# BWE# CLK
D
Q
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
BWd#
D
Q
byte d write byte b write byte a write DQa,DQb DQc,DQd byte b write Output Buffers DQa,D Qb byte c write byte a write 512K x 9 x 2 SRAM Array Output Buffers
CE# CE2
[2]
ENABLE
D
Q
CE2# OE# ZZ Power Down Logic Input Register
16
ADSP# A
Address Register 256K x 9 x 4 SRAM Array
BYTE b WRITE
ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic
512K x 18 (CY7C1363A/GVT71512B18)Functional Block Diagram
BWb# BWE#
D
Q
BYTE a WRITE
BWa# GW# CE# CE2
[2]CE2#
D
Q
ENABLE
D
Power Down Logic
Q
ZZ OE# ADSP#
Input Register
17
A
Address Register
ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic
Notes: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information. 2. CE2 is for AJ/TA version only.
2
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Pin Configurations
T(AJ) Package Version CY7C1361A/GVT71256B36 256Kx36 100-Pin TQFP
TA(A) Package Version
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100-pin TQFP
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
A A CE# CE2 BWd# BWc# BWb# BWa# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A
A A CE# CE2 BWd# BWc# BWb# BWa# A VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A
DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100-pin TQFP TA version
DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa
CY7C1363A/GVT71512B18 T(AJ) Package Version 512Kx18 100-Pin TQFP
A A CE# CE2 NC NC BWb# BWa# A VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A
10 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100-pin TQFP
A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb NC VCC NC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC
A A CE# CE2 NC NC BWb# BWa# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A A
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
TA(A) Package Version
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67
100-pin TQFP TA version
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC
MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A
3
MODE A A A A A1 A0 NC NC VSS VCC NC A A A A A A A A
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Pin Configurations (continued)
CY7C1361A/GVT71256B36 256Kx36 119-Ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ
CY7C1361A/GVT71256B36 512Kx18 119-Ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQb NC VCCQ NC DQb VCCQ NC DQb VCCQ DQb NC NC NC VCCQ 2 A CE2 A NC DQb NC DQb NC VCC DQb NC DQb NC DQb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQa NC DQa NC DQa VCC NC DQa NC DQa NC A A NC 7 VCCQ NC NC NC DQa VCCQ DQa NC VCCQ DQa NC VCCQ NC DQa NC ZZ VCCQ
4
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions
x36 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T x36 QFP Pins 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 92 (A/T version) 43 (AJ/TA version) 93 94 95 96 87 Pin Name A0 A1 A Type InputSynchronous Description Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle.
5L 5G 3G 3L 4M
BWa BWb BWc BWd BWE
InputSynchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit WRITE to occur independent of the BWE and BWn lines and must meet the set up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device . and to gate ADSP Chip Enable: This active HIGH input is used to enable the device. Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. A NC or HIGH on this pin selects interleaved burst. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect).
InputSynchronous InputSynchronous InputSynchronous
4H
88
GW
4K
89
CLK
4E 2B (not available for PBGA) 4F 4G
98 97 92 (for AJ/TA version only) 86 83
CE CE2 CE2 OE ADV
InputSynchronous InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous InputSynchronous
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
InputStatic InputAsynchronous
7T
64
ZZ
5
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions (continued)
x36 PBGA Pins (a) 6P 7P 7N, ,, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G, 6F, 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P 2P , 2U 3U 4U x36 QFP Pins (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 38 39 43 for BG/B and A/T version 42 for BG/B and A/T version 15, 41,65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 14, 16, 66 38, 39, 42 for AJ/TA Version Pin Name DQa DQb DQc DQd Type Input/ Output Description Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb. Third Byte is DQc. Fourth Byte is DQd. Input data must meet set up and hold times around the rising edge of CLK.
TMS TDI TCK
Input
IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for AJ/TA package version.
5U
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for AJ/TA package version. Core power Supply: +3.3V -5% and +10% Ground: GND.
4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P 5P , 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 6U
VCC VSS
Supply Ground
VCCQ
I/O Supply
Output Buffer Supply: +2.5V or +3.3V.
NC
-
No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS.
512K X 18 Pin Descriptions
x18 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T X18 QFP Pins 37 36 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 92 (A/T version) 43 (AJ/TA version) 93 94 Pin Name A0 A1 A Type InputSynchronous Description Addresses: These inputs are registered and must meet the set up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle.
5L 3G
BWa BWb
InputSynchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa. BWb controls DQb. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte write operations and must meet the set up and hold times around the rising edge of CLK.
4M
87
BWE
InputSynchronous
6
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
512K X 18 Pin Descriptions (continued)
x18 PBGA Pins 4H X18 QFP Pins 88 Pin Name GW Type InputSynchronous InputSynchronous Description Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the BWE# and WEn# lines and must meet the set up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set up and hold times around the clock's rising edge. Chip Enable: This active LOW input is used to enable the device . and to gate ADSP Chip Enable: This active HIGH input is used to enable the device. Chip Elnable: This active LOW input is used to enable the device. Not available for B and T package versions. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with CE being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. A NC or HIGH on this pin selects interleaved burst. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input data must meet setup and hold times around the rising edge of CLK.
4K
89
CLK
4E 2B (not available for PBGA) 4F 4G
98 97 92 (for AJ/TA Version only) 86 83
CE CE2 CE2 OE ADV
InputSynchronous inputSynchronous inputSynchronous Input InputSynchronous InputSynchronous InputSynchronous
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
InputStatic Input-Asynchronous Input/ Output
7T
64
ZZ
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 2U 3U 4U
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 38 39 43 for B and T version 42 for B and T version 15, 41,65, 91 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
DQa DQb
TMS TDI TCK
Input
IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for AJ/TA package version.
5U
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for AJ/TA package version. Core power Supply: +3.3V -5% and +10% Ground: GND.
4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P 5P ,
VCC VSS
Supply Ground
7
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
512K X 18 Pin Descriptions (continued)
x18 PBGA Pins 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P 6P 1R, 5R, ,, 7R, 1T, 4T, 6U X18 QFP Pins 4, 11, 20, 27, 54, 61, 70, 77 1-3, 6, 7, 14, 16, 25, 28-30, 5153, 56, 57, 66, 75, 78, 79, 80, 95, 96 38, 39, 42 for AJ/TA version Pin Name VCCQ Type I/O Supply Description Output Buffer Supply: +2.5V or +3.3V.
NC
-
No Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS.
Burst Address Table (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
8
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Truth Table[3, 4, 5, 6, 7, 8, 9]
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current
Current Current
CE H L L L L L L L L L X X H H X H X X H H
X H
CE2 X X H X H L L L L L X X X X X X X X X X
X X
CE2 X L X L X H H H H H X X X X X X X X X X
X X
ADSP X L L H H L L H H H H H X X H X H H X X
H X
ADSC L X X L L X X L L L H H H H H H H H H H
H H
ADV X X X X X X X X X X L L L L L L H H H H
H H
WRITE X X X X X X X L H H H H H H L L H H H H
L L
OE X X X X X L H X L H L H L H X X L H L H
X X
CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
L-H L-H
DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z
D D
Partial Truth Table for Read/Write[10]
FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X
Notes: 3. X = "Don't Care." H = logic HIGH. L = logic LOW. For x36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. For x18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH. 4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd. 5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 6. Suspending burst generates wait cycle. 7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 9. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. 10. For X18 product, There are only BWa and BWb.
9
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview This device incorporates a Serial Boundary Scan Access Port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
Test Access Port (TAP) Registers
Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for x36 device and 51 bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit's position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name, the third column is the TQFP pin number, and the fourth column is the PBGA bump number.
Test Access Port (TAP)
TCK - Test Clock (Input) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS - Test Mode Select (Input) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TDI - Test Data In (Input) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 2.) TDO - Test Data Out (Output) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.)
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device's input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use.
TAP Controller Instruction Set
Overview There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
REUN-TEST/ IDLE
1
SELECT DR-SCAN 0 1
1
Figure 1. TAP Controller State Diagram[11]
Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
x
.
.
.
.
2
1
0
Boundary Scan Register [12]
TDI TAP Controller TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20C < Tj < 110C; VCC = 3.3V -0.2V and +0.3V unless otherwise noted)
Parameter VIH VIl ILI ILI ILO VOLC VOHC VOLT VOHT Description Input High (Logic 1) Voltage[13, 14] Input Low (Logic 0) Voltage[13, 14] 0V < VIN < VCC 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100 A IOHC = 100 A IOLT = 8.0 mA IOHT = 8.0 mA 2.4 VCC - 0.2 0.4 Input Leakage Current TMS and TDI input Leakage Current Output Leakage Current LVCMOS Output Low Voltage[13, 15] LVCMOS Output High Voltage[13, 15] LVTTL Output Low LVTTL Output High Voltage[13] Voltage[13] Test Conditions Min. 2.0 -0.3 -5.0 -30 -5.0 Max. VCC + 0.3 0.8 5.0 30 5.0 0.2 Unit V V A A A V V V V
Notes: 12. X = 69 for the x36 configuration; X = 50 for the x18 configuration. 13. All Voltage referenced to VSS (GND). 14. Overshoot: VIH(AC)13
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
TAP AC Switching Characteristics Over the Operating Range[16, 17]
Parameter Clock tTHTH fTF tTHTL tTLTH Output Times tTLQX tTLQV tDVTH tTHDX Set-up Times tMVTH tCS Hold Times tTHMX tCH TMS Hold Capture Hold 5 5 ns ns TMS Set-Up Capture Set-Up 5 5 ns ns TCK LOW to TDO Unknown TCK LOW to TDO Valid TDI Valid to TCK HIGH TCK HIGH to TDI Invalid 5 5 0 10 ns ns ns ns Clock Cycle Time Clock Frequency Clock HIGH Time Clock LOW Time 8 8 20 50 ns MHz ns ns Description Min. Max. Unit
Notes: 16. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 17. Test conditions are specified using the load in TAP AC Test Conditions.
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TAP Timing and Test Conditions
1.5V 50 TDO Z0 =50 CL =20 pF VSS 3.0V 1.5V
1.5 ns 1.5 ns
ALL INPUT PULSES
GND
(a)
tT H T H
t
THTL
t
TLTH
TEST CLOCK (TCK)
tM V T H tT H M X
TEST MODE SELECT (TMS)
tD V T H tT H D X
TEST DATA IN (TDI)
tT L Q V tT L Q X
TEST DATA OUT (TDO)
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Identification Register Definitions
Instruction Field REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) RESERVED (17:12) CYPRESS JEDEC ID CODE (11:1) ID Register Presence Indicator (0) 256K x 36 XXXX 00110 00100 XXXXXX 00011100100 1 512K x 18 XXXX 00111 00011 XXXXXX 00011100100 1 Description Reserved for revision number. Defines depth of 256K or 512K words. Defines width of x36 or x18 bits. Reserved for future use. Allows unique identification of DEVICE vendor. Indicates the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x36) 3 1 32 70 Bit Size (x18) 3 1 32 51
Instruction Codes
Instruction EXTEST 000 Code Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. This instruction is not IEEE 1149.1-compliant. Preloads ID register with vendor ID code and places it between TDI and TDO. This instruction does not affect device operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all device outputs to High-Z state. Do not use these instructions; they are reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not affect device operations. This instruction does not implement IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations.
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Boundary Scan Order (256K x 36)
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name A A A A A A A DQa DQa DQa DQa DQa DQa DQa DQa DQa ZZ DQb DQb DQb DQb DQb DQb DQb DQb DQb A A ADV ADSP ADSC OE BWE GW CLK TQFP 44 45 46 47 48 49 50 51 52 53 56 57 58 59 62 63 64 68 69 72 73 74 75 78 79 80 81 82 83 84 85 86 87 88 89 Bump ID 2R 3T 4T 5T 6R 3B 5B 6P 7N 6M 7L 6K 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 7H 6G 6E 7D 6A 5A 4G 4A 4B 4F 4M 4H 4K
Boundary Scan Order (256K x 36) (continued)
Bit# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name A BWa BWb BWc BWd CE2 CE A A DQc DQc DQc DQc DQc DQc DQc DQc DQc NC DQd DQd DQd DQd DQd DQd DQd DQd DQd MODE A A A A A1 A0 TQFP 92 93 94 95 96 97 98 99 100 1 2 3 6 7 8 9 12 13 14 18 19 22 23 24 25 28 29 30 31 32 33 34 35 36 37 Bump ID 6B 5L 5G 3G 3L 2B 4E 3A 2A 2D 1E 2F 1G 2H 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 1K 2L 2N 1P 3R 2C 3C 5C 6C 4N 4P
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Boundary Scan Order (512K x 18)
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Signal Name A A A A A A A DQa DQa DQa DQa ZZ DQa DQa DQa DQa DQa A A A ADV ADSP ADSC OE BWE GW TQFP 44 45 46 47 48 49 50 58 59 62 63 64 68 69 72 73 74 80 81 82 83 84 85 86 87 88 Bump ID 2R 2T 3T 5T 6R 3B 5B 7P 6N 6L 7K 7T 6H 7G 6F 7E 6D 6T 6A 5A 4G 4A 4B 4F 4M 4H
Boundary Scan Order (512K x 18) (continued)
Bit# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal Name CLK A BWa BWb CE2 CE A A DQb DQb DQb DQb NC DQb DQb DQb DQb DQb MODE A A A A A1 A0 TQFP 89 92 93 94 97 98 99 100 8 9 12 13 14 18 19 22 23 24 31 32 33 34 35 36 37 Bump ID 4K 6B 5L 3G 2B 4E 3A 2A 1D 2E 2G 1H 5R 2K 1L 2M 1N 2P 3R 2C 3C 5C 6C 4N 4P
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines only, not tested.) Voltage on VCC Supply Relative to VSS ......... -0.5V to +4.6V VIN ............................................................-0.5V to VCC+0.5V Storage Temperature (plastic)........................-55C to +150 Junction Temperature ...................................................+150 Power Dissipation .......................................................... 1.0W Short Circuit Output Current ....................................... 50 mA
.
Operating Range
Range Com'l Ind'l Ambient Temperature[10] 0C to +70C -40C to +85C VCC 3.3V -5%/+10%
Electrical Characteristics Over the Operating Range
Parameter VIHD VIH VIl ILI ILI ILO VOH VOL VCC VCCQ VCCQ Parameter ICC Input Low (Logic 0) Voltage[13, 19] 0V < VIN < VCC 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -5.0 mA IOL = 8.0 mA 3.135 3.135 2.375 (2.5V)[13] Input Leakage Current[13, 19] MODE and ZZ Input Leakage Current[20] Output Leakage Current Output High Output Low Supply Voltage[13] Voltage[13] Description Input High (Logic 1) Voltage[13, 19] Test Conditions Data Inputs (DQx) All Other Inputs Min. 2.0 2.0 -0.5 -5 -30 -5 2.4 0.4 3.6 VCC VCC -7 320 -8 270 Max. VCC+0.3 4.6 0.8 5 30 5 Unit V V V A A A V V V V V
Voltage[13]
I/O Supply Voltage (3.3V)[13] I/O Supply Voltage
Description Power Supply Current: Operating[21, 22, 23]
Conditions Device selected; all inputs < VILor > VIH; cycle time > tKC Min.; VCC = Max.; outputs open Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC - 0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC Min.
Typ. 150
-6 400
-6.5 360
Unit mA
ISB2
CMOS Standby[22, 23]
5
10
10
10
10
mA
ISB3
TTL Standby[22, 23]
15
30
30
30
30
mA
ISB4
Clock Running[22, 23]
40
90
80
70
60
mA
Thermal Consideration
Parameter JA JC Description Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case Conditions Still air, soldered on 4.25 x 1.125 inch 4-layer PCB TQFP Typ. 25 9 Unit C/W C/W
Notes: 18. TA is the case temperature. 19. Overshoot: VIH < +6.0V for t < tKC /2. Undershoot: VIL < -2.0V for t < tKC /2. 20. Output loading is specified with CL= 5 pF as in AC Test Loads. 21. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 22. "Device Deselected" means the device is in Power-Down mode as defined in the truth table. "Device Selected" means the device is active. 23. Typical values are measured at 3.3V, 25C and 20-ns cycle time.
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Capacitance
Parameter CI CO Input Description Capacitance[15]
[15]
Test Conditions TA = 25C, f = 1 MHz, VCC= 3.3V
Typ. 5 7
Max. 7 8
Unit pF pF
Input/Output Capacitance (DQ)
Typical Output Buffer Characteristics
Output High Voltage VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4 Pull-up Current IOH (mA) Min. ) -38 -38 -38 -26 -20 0 0 0 0 IOH (mA) Max. -105 -105 -105 -83 -70 -30 -10 0 0 Output Low Voltage VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 Pull-down Current IOL (mA) Min. 0 0 10 20 31 40 40 40 40 IL (mA) Max. ) 0 0 20 40 63 80 80 80 80
AC Test Loads and Waveforms (3.3V I/O)
DQ Z0 = 50 RL = 50 R = 351 Vt = 1.5V 5 pF 3.3V DQ R = 317 ALL INPUT PULSES 3.0V 10% 0V 1.0 ns 90%
[13]
90% 10% 1.0 ns
(a)
(b)
(c)
AC Test Loads and Waveforms (2.5V I/O)
DQ Z0 = 50 2.5V RL = 50 Vt = 1.25V 10% 0V 1.0 ns ALL INPUT PULSES 90% 90% 10% 1.0 ns
(a)
(c)
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Switching Characteristics Over the Operating Range[24]
150 MHz -6 Parameter Clock tKC tKH tKL Clock Cycle Time Clock HIGH Time Clock LOW Time 6.7 2.5 2.5 7.5 2.5 2.5 8.5 3.0 3.0 10 3.5 3.5 ns ns ns Description Min. Max. 133 MHz -6.5 Min. Max. 117 MHz -7 Min. Max. 100 MHz -8 Min. Max. Unit
Output Times tKQ Clock to Output Valid
VCCQ = 3.3V VCCQ = 2.5V
6.0 6.5 2 0 2 3.5 3.5 4.5 0 3.5 0 2 0 2
6.5 7.0 2 0 3.5 3.5 4.5 0 3.5 2
7.0 7.5 2 0 3.5 3.5 4.5 0 3.5 2
8.0 9.0
ns ns ns ns
tKQX tKQLZ tKQHZ tOEQ
Clock to Output Invalid Clock to Output in Low-Z[15, 20, 25] Clock to Output in OE to Output High-Z[15, 20, 25]
VCCQ = 3.3V VCCQ = 2.5V
3.5 4.0 5.0
ns ns ns ns
Valid[26]
tOELZ tOEHZ
OE to Output in Low-Z[15, 20, 25] OE to Output in High-Z[15, 20, 25]
3.5
ns
Set-Up Times tS Hold Times tH Address, Controls and Data In[27] 0.5 0.5 0.5 0.5 ns Address, Controls and Data In[27] 1.5 1.5 1.8 2.0 ns
Notes: 24. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. 25. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 26. OE is a "Don't Care" when a byte write enable is sampled LOW. 27. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for "Don't Care" as defined in the truth table.
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Timing Diagrams
Read Timing[28, 29]
tKC tKL
CLK
tS tKH
ADSP#
tH
ADSC#
tS
ADDRESS BWa#, BWb#, BWc#, BWd#,[29] BWE#, GW# CE#[30]
A1
tH
A2
tS
ADV#
tH
OE#
tKQ tKQLZ tOELZ
Q(A1)
tOEQ
tKQ
Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2)
DQ
SINGLE READ
BURST READ
Notes: 28. For X18 product, there are only BWa and BWb for byte write control. 29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
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Timing Diagrams (continued)
Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS BWa#, BWb#, BWc#, BWd#,[29] BWE# GW# CE#[30]
A1
tH
A2
A3
tS
ADV#
tH
OE#
tKQX tOEHZ
D(A1) D(A2) D(A2+2) D(A2+2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
DQ
Q
SINGLE WRITE
BURST WRITE
BURST WRITE
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Timing Diagrams (continued)
Read/Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS BWa#, BWb#, BWc#, BWd#, [29] BWE#, GW# CE#[30]
A1
A2
tH
A3
A4
A5
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Burst Read
Burst Write
Ordering Information
Speed (MHz) 150 Ordering Code CY7C1361A-150AC GVT71256B36TA-6 CY7C1361A-150AJC GVT71256B36T-6 CY7C1361A-150BGC GVT71256B36B-6 133 CY7C1361A-133AC GVT71256B36TA-6.5 CY7C1361A-133AJC GVT71256B36T-6.5 CY7C1361A-133BGC GVT71256B36B-6.5 BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack Commercial BG119 119-Ball BGA Package Name A101 Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Ordering Information (continued)
Speed (MHz) 117 Ordering Code CY7C1361A-117AC GVT71256B36TA-7 CY7C1361A-117AI GVT71256B36TA-7I CY7C1361A-117AJC GVT71256B36T-7 CY7C1361A-117AJI GVT71256B36T-7I CY7C1361A-117BGC GVT71256B36B-7 CY7C1361A-117BGI GVT71256B36B-7I 100 CY7C1361A-100AC GVT71256B36TA-8 CY7C1361A-100AI GVT71256B36TA-8I CY7C1361A-100AJC GVT71256B36T-8 CY7C1361A-100AJI GVT71256B36T-8I CY7C1361A-100BGC GVT71256B36B-8 CY7C1361A-100BGI GVT71256B36B-8I 150 CY7C1363A-150AC GVT71512B18TA-6 CY7C1363A-150AJC GVT71512B18T-6 CY7C1363A-150BGC GVT71512B18B-6 133 CY7C1363A-133AC GVT71512B18TA-6.5 CY7C1363A-133AJC GVT71512B18T-6.5 CY7C1363A-133BGC GVT71512B18B-6.5 BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack Commercial BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack Commercial Industrial BG119 119-Ball BGA Commercial Industrial Commercial Industrial A101 100-Lead Thin Quad Flat Pack Commercial Industrial BG119 119-Ball BGA Commercial Industrial Commercial Industrial Package Name A101 Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
25
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Ordering Information (continued)
Speed (MHz) 117 Ordering Code CY7C1363A-177AC GVT71512B18TA-7 CY7C1363A-177AI GVT71512B18TA-7I CY7C1363A-177AJC GVT71512B18T-7 CY7C1363A-177AJI GVT71512B18T-7I CY7C1363A-177BGC GVT71512B18B-7 CY7C1363A-177BGI GVT71512B18B-7I 100 CY7C1363A-100AC GVT71512B18TA-8 CY7C1363A-100AI GVT71512B18TA-8I CY7C1363A-100AJC GVT71512B18T-8 CY7C1363A-100AJI GVT71512B18T-8I CY7C1363A-100BGC GVT71512B18B-8 CY7C1363A-100BGI GVT71512B18B-8I Document #: 38-00991-*A Industrial BG119 119-Ball BGA Commercial Industrial Commercial Industrial A101 100-Lead Thin Quad Flat Pack Commercial Industrial BG119 119-Ball BGA Commercial Industrial Commercial Industrial Package Name A101 Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
26
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
27
CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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